In an electrically programmable non-volatile semiconductor memory, such as a flash memory, a logic state is stored with a threshold voltage (hereinafter referred to as `cell Vt`) of a memory cell. For example, in storing binary information, data "0" can be represented by a cell Vt lowered by erase operation and data "1" can be represented by a cell Vt raised by write operation. Also, multi-valued information is stored in like manner. For example, in storing ternary information, data "0" can be represented by a cell Vt lowered by erase operation, and data "1", "2" can be represented by cell Vt's raised stepwise by write operation. On the contrary, in storing binary information, data "1" can be represented by a cell Vt raised by erase operation and data "0" can be represented by a cell Vt lowered by write operation. In like manner, in storing ternary information, data "2" can be represented by a cell Vt raised by erase operation, and data "1", "0" can be represented by cell Vt's lowered stepwise by write operation. The former example is taken for a channel hot electron (CHE) write type memory cell, and the latter example is taken for a Faurer-Nordheim (FN) write type memory cell.
In such a flash memory, in general, writing of data is conducted by one bit while checking a write state (cell Vt) and erasing of data is conducted by a group of memory cells (block) more than that of writing while checking an erase state (cell Vt) . In flash memories, cell Vt's are properly set corresponding to data "0", "1" and "2" in writing of data. However, a cell Vt may be changed by various disturbances and a leakage current from a charge-storage layer, thereby deteriorating or destroying the stored data.
Several methods of restoring a cell Vt to the original value (cell Vt just after writing) while detecting a change (deterioration) of cell Vt to prevent stored data from being destroyed have been proposed.
For example, Japanese patent application laid-open No.8-77785(1996) discloses a method and circuit that, in writing multi-valued information, a change in cell Vt (deterioration of stored data) is detected by applying different voltages to a word line and rewriting of data is then conducted to restore a cell Vt to the original value. Also, Japanese patent application laid-open No.8-249893(1996) discloses a method and circuit that, in writing multi-valued information, several detecting means for checking the insufficiency or excess of writing after the write operation are provided, and additional writing is conducted to a insufficient write cell or rewriting or additional erasing is conducted to an excessive write cell after erasing the memory cell.
Furthermore, Japanese patent application laid-open No.8-235887(1996) discloses a method that, in storing binary information, the deterioration of data stored in memory cell is detected by using two reference levels for verification provided other than a normal reference value for reading out, and the contents are transferred to a register and then rewriting is conducted when it is judged that the data restoring is necessary.
However, the conventional data restoring methods have some problems. First, the chip area has to be increased due to the excessive writing that requires registers of a same number as the number of the memory cells of an erase block. Second, the data restoring speed has to be reduced due to the data transfer time to the registers. Namely, when a memory cell of excessive writing is detected, all memory cells in an erase block have to be erased in a normal manner (initialization of stored data) and then the data (data to be rewritten) stored in the original memory cells have to be temporarily transferred outside the memory cells before the rewriting.